BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 137 Power Management Document 5722-PG101-R
The following functional blocks are integral to MAC power management:
• PMSCR register
• PCI Clock Control register
• Miscellaneous Control register
• WOL
• PCI Vaux Supply
• PCI Slot Power Supply
• GPIO
OPERATIONAL CHARACTERISTICS
Figure 55 applies to the BCM5722 Ethernet controller reference designs. The MAC GPIO pins are available for application
specific usage; however, Broadcom encourages both software and hardware engineers to follow the Broadcom design
guidelines and application notes. NIC and LOM designs use external board level logic to switch power regulators for D3 ACPI
mode.
Figure 55: Power State Transition Diagram
Device State D0 (Uninitialized)
The D0 state is entered after a PCI reset or device (software) reset. The assertion of PME causes the PCI bridge to drive
RST
. The MAC hardware blocks are not initialized in this state. For example, the RX engine, TX engine, multicast filter, and
memory arbiter are all uninitialized. All the MAC functional blocks are powered.
D0
Unitialized
D3 Cold
(PME
Enabled)
D3 Hot
D0
Active
PCI Slot
(3.3v or 5.0v) Power
Removed
PME Asserted
or
Hardware reset
PCI I/O Pins Powered
from PCI Vaux Supply
Device driver
initializes state
machines,
memory arbiter,
and so on
Device driver sets
PMCSR register to
power state D3
and
GPIO0, 1, and 2
PME Asserted
or
Software reset
PCI I/O Pins Powered
from PCI Slot Supply
Other I/O functions and
core logic powered
from PCI Vaux
Device driver sets
PMCSR register
to power state D3
and
GPIO0, 1, and 2
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