Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers (BCM5906/BCM5906M) Page 502
Auxiliary Mode 2 Register
10BT Dribble Bit Correct
When enabled, the PHY rounds-down to the nearest nibble when dribble bits are present on the 10BASET input stream.
Jumbo Packet Mode
When enabled, the 100BASE-X unlock timer changes to allow long packets.
Jumbo Packet FIFO Enable
When enabled, the receive FIFO doubles from 7 nibbles to 14 nibbles. The Jumbo Packet FIFO Enable bit should be set to
a 1 when jumbo packet mode is enabled.
Block 10BT Echo Mode
When enabled, during 10BASE-T half-duplex transmit operation, the TXEN signal does not echo onto the RXDV signal. The
TXEN echoes onto the CRS signal and the CRS deassertion directly follows the TXEN deassertion.
Table 554: Auxiliary Mode 2 Register (Address 27d, 1Bh)
BIt Name R/W Description Default
15:12 Reserved - - 0
11 10BT Dribble Bit Correct R/W 1 = Enable
0 = Disable
0
10 Jumbo Packet Mode R/W 1 = Enable
0 = Disable
0
9 Jumbo Packet FIFO Enable R/W 1 = Enable
0 = Disable
0
8 Reserved - - 0
7 Block 10BT Echo Mode R/W 1 = Enable
0 = Disable
1
6 Traffic Meter LED Mode R/W 1 = Enable
0 = Disable
0
5 Activity LED Force On R/W 1 = ON
0 = Normal operation
0
4 Serial LED Mode (this bit is available
only in PHY 1 of 8)
R/W 1 = Enable Serial LED mode 0
3 Reserved - - 1
2 Activity/Link LED Mode R/W 1 = Enable
0 = Disable
0
1 Qual Parallel Detect Mode R/W 1 = Enable
0 = Disable
1
0 Reserved - - 0
R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear after read
operation. Use default values of reserved bit(s) when writing to reserved bit(s).
To Next Page
Loading...