BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 331 Message Signaled Interrupt Registers Document 5722-PG101-R
MSI FIFO ACCESS REGISTER (OFFSET 0X6008)
The MSI FIFO Access Register is used to give an MSI request to the PCI block. The actual MSI data is indicated in the
bottom bits. If the MSI is properly enqueued into the FIFO, the overflow bit remains cleared. If the FIFO overflowed, the bit
is set and must be written to be cleared. If the overflow bit is set when the access register is written, no MSI is enqueued.
Table 339: MSI FIFO Access Register (Offset 0x6008)
Bit Field Description Init Access
31:4 Reserved Always 0. 0 RO
3 Overflow No space left in FIFO. 0 W2C
2:0 MSI Data Indicates which of the (up to eight) MSIs to use. 0 W/O
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