Broadcom BCM5722 - Table 261: Receive List Placement Statistics Enable Mask Register (Offset 0 X2018)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Receive List Placement Control Registers Page 284
RECEIVE LIST PLACEMENT STATISTICS ENABLE MASK REGISTER (OFFSET 0X2018)
Table 261: Receive List Placement Statistics Enable Mask Register (Offset 0x2018)
Bit Field Description Init Access
31:26 Reserved – 0 RO
25 RSS_Priority (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
This bit enables the receive packet to choose receive return ring
in terms of RSS hash value instead of RC class when both RSS
and RC rules are matched. Default is to give priority to RC.
0x0 R/W
Reserved (other devices) 0x0 RO
24 RC Return Ring Enable
(BCM5722, BCM5755,
BCM5755M, BCM5756M,
BCM5757 only)
• 1 = Enable receive packet to use RC rule class as return ring
number if RC rule is matched. This bit will be used in
conjunction with bit25 to derive the final receive return ring.
• 0 = Disable receive packet to use RC rule class as return ring
number. Receive packet only uses RSS hash to select the
receive return ring. If no any RSS hash types are applied, the
default ring 0 will be used.
This bit should be configured to be 0 for normal function.
0x0 R/W
Reserved (other devices) 0x0 RO
23 CPU MACTQ Priority Disable
(BCM5722, BCM5755,
BCM5755M, BCM5756M,
BCM5757 only)
• 1 = Disable CPU priority over SDC when arbitrating the
MACTQ write requests
• 0 = Enable CPU priority over SDC when arbitrating the
MACTQ write requests
0x0 R/W
Reserved (other devices) 0x0 RO
22:19 Reserved – 0 RO
18 Disable MACTQ Double Ack
Issue Fix
Disable MACTQ double Ack issue fix (CQ9987).
• 1: Disabled
• 0: Enabled
1R/W
17:2 ASIC Revision ID See “Revision Levels” on page 8.R/W
1 Disable ASF Lockup Issue Fix Disable ASF lockup fix (CQ 9365).
• 1: Disabled
• 0: Enabled
1R/W
0 Reserved – 0 RO