Broadcom BCM5722 - Broadcom Mask Mode; Broadcom Tagged Status Mode; Clear Ticks on BD Events Mode; No Interrupt on DMAD Force

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 185 Other Configuration Controls Document 5722-PG101-R
OTHER CONFIGURATION CONTROLS
BROADCOM MASK MODE
Enabled by setting the Mask_Interrupt_Mode bit (bit 8) of the Miscellaneous Host Control register (see “Miscellaneous Host
Control Register (Offset 0x68)” on page 204). When enabled, setting the mask bit of the Miscellaneous Host Control register
will mask (de-assert) the INTA
signal at the pin, but it will not clear the interrupt state and it will not latch the INTA value.
Clearing the mask bit will enable the interrupt state to propagate to the INTA
signal. Note that the During Interrupt
Coalescence registers are only used when the Mailbox 0 is set.
BROADCOM TAGGED STATUS MODE
Enabled by setting the Status Tagged Status Mode bit of the Miscellaneous Host Control register (see “Miscellaneous Host
Control Register (Offset 0x68)” on page 204). When enabled, a unique eight-bit tag value will be inserted into the Status
Block Status Tag at location 7:0. The Status Tag can be returned to the Mailbox 0 register at location 31:24 by the host driver.
When the Mailbox 0 register field 23:0 is written with a zero value, the tag field of the Mailbox 0 register is compared with
the tag field of the last Status Block to be DMAed to the host. If the tag returned is not equivalent to the tag of the first Status
Block DMAed, the interrupt status is entered.
CLEAR TICKS ON BD EVENTS MODE
Enabled by setting the Clear Ticks Mode on RX or the Clear Ticks Mode on TX bits of the Host Coalescing Mode register
(see “Host Coalescing Mode Register (Offset 0x3C00)” on page 294). When enabled, the counters initialize to the idle state
and begin counting only after a receive or transmit BD event is detected.
NO INTERRUPT ON FORCE UPDATE
Enabled by setting the No Interrupt on Force bit of the Host Coalescing Mode register (see “Host Coalescing Mode Register
(Offset 0x3C00)” on page 294). When enabled, writing the Force update bit of the Host Coalescing Mode register will cause
a status block update without a corresponding interrupt event.
NO INTERRUPT ON DMAD FORCE
Enabled by setting the No Interrupt on DMAD force bit of the Host Coalescing Mode register (see “Host Coalescing Mode
Register (Offset 0x3C00)” on page 294). When enabled, the BD_FLAG_COAL_NOW bit of the buffer descriptor may be set
to force a status block update without a corresponding interrupt.