Broadcom BCM5722 - Table 129: PCI Clock Control Register

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 207 Broadcom Vendor-Specific Capabilities Document 5722-PG101-R
PCI CLOCK CONTROL REGISTER (OFFSET 0X74)
Note: The Enable Clock Control Register Read/Write Capability bit of the Miscellaneous Host Control register
must be enabled to write the PCI Clock Control register from the PCI configuration cycle (see “Miscellaneous
Host Control Register (Offset 0x68)” on page 204).
Table 129: PCI Clock Control Register
Bit Description Description Init Access
31 PLP Clock Disable When this bit is set to 1, PCIe Physical Layer Clock is
disabled.
0
1 in CWOL
R/W
30 DLP Clock Disable When this bit is set to 1, PCIe Data Link Layer Clock is
disabled.
0
1 in
CWOL
R/W
29 TLP Clock Disable When this bit is set to 1, PCIe Transaction Layer Clock
is disabled Once this bit is set, the FW can no longer
access the PCI Config registers (including the clock
control register), so it should be set only when the FW
has no need to access the clock control and other PCI
config registers until next power cycle.
0 R/W
28 PCIe Clock to Core Clock When this bit is 1, the source of internal PCIe Clock is
CORE_CLK.
0
1 in
CWOL
R/W
27 Reserved – 0 RO
26 PCI Read Too Long ECO
Fix
When this bit is 1, it enables the fix for the PCI read 8
extra bytes during LSO.
0 R/W
25 PCI Write Too Long ECO Fix When this bit is 1, it enables the fix for PCI write 8 extra
bytes during slow core clock.
0 R/W
24 Select TEST CLK Source Selects the following test clocks:
• 0 = CLK125 (125-MHz clock from GPHYPLL).
• 1 = TLP CLK (/4 of the SerDes clock).
0 R/W
23 Select TEST CLK When this bit is 1, the GPHYPLL test clock is muxed out
to the GPIO0 pin.
0 R/W
22 TPM_CORE_CLK Disable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
When this bit is 1, the CORE_CLK to TPM block is
disabled.
0R/W
Reserved (other devices) – 0 RO
21 Force CLKRUN When the bit is 1, the PCI/Cardbus clock will be forced
to maintain the PCI clock.
N/A for PCIe Device.
0R/W
20 Select Final Alt Clock Select the 6.25-MHz clock as the alternate clock (use in
Airplane Mode). If this bit is 0, the alternate clock will be
selected by bit 13.
0 R/W
19 Slow Core Clock Mode Set this bit to 1 when running a 10:1 PCI to Core clock
ratio. For engineering debug only.
0 R/W
Reserved (BCM5906 only) – 0 RO