Broadcom BCM5722 - Table 336: Message Signaled Registers; Table 337: MSI Mode Register (Offset 0 X6000); Table 338: MSI Status Register (Offset 0 X6004)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Message Signaled Interrupt Registers Page 330
MESSAGE SIGNALED INTERRUPT REGISTERS
MSI MODE REGISTER (OFFSET 0X6000)
MSI STATUS REGISTER (OFFSET 0X6004)
Table 336: Message Signaled Registers
Offset Registers
0x6000–0x6003 MSI Mode Register
0x6004–0x6007 MSI Status Register
0x6008–0x600b MSI FIFO Access Register
0x600C–0x67FF Reserved
Table 337: MSI Mode Register (Offset 0x6000)
Bit Field Description Init Access
31:7 Reserved – 0 RO
6 MSI FIFO Overrun Attn MSI FIFO overrun attention enable. 0 R/W
5 MSI FIFO Underrun
Attn
MSI FIFO underrun attention enable. 0 R/W
4 PCI Parity Error Attn PCI parity error attention enable. 0 R/W
3 PCI Master Abort Attn PCI master abort attention enable. 0 R/W
2 PCI Target Abort Attn PCI target abort attention enable. 0 R/W
1 Enable This bit controls whether the MSI state machine is active
or not. When set to 0, it completes the current operation
and cleanly halts. Until it is completely halted, it remains
one when read.
1R/W
0 Reset When this bit is set to 1, the MSI state machine is reset.
This is a self-clearing bit.
0R/W
Table 338: MSI Status Register (Offset 0x6004)
Bit Field Description Init Access
31:7 Reserved – 0 RO
6 MSI FIFO Overrun MSI FIFO overrun status 0 W2C
5 MSI FIFO Underrun MSI FIFO underrun status 0 W2C
4 PCI Parity Error PCI parity error status 0 W2C
3 PCI Master Abort PCI master abort status 0 W2C
2 PCI Target Abort PCI target abort status 0 W2C
1:0 Reserved – 0 RO