Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers (BCM5906/BCM5906M) Page 482
To put a transceiver with PHY address 00001 into loopback mode, the following MII write instruction must be issued:
1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1...
To determine if a PHY is in the link pass state, the following MII read instruction must be issued:
1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 ZZ ZZZZ ZZZZ ZZZZ ZZZZ 1...
For the MII read operation, the PHY core drives the MDIO line during the TA and Data fields (the last 17 bit times). A final
65th clock pulse must be sent to close the transaction and cause a write operation to take place.
MII REGISTER MAP SUMMARY
The MII register map summary for each port of the PHY core. The register addresses are specified in decimal and in hex
form, and the name of register bits abbreviated when easier to understand. When writing to any register, preserve existing
values of the reserved bits by completing a Read/Modify Write. Ignore reserved bits when reading registers. Never write to
an undefined register.
The reset values of the registers are shown in the Default column. Some of these values could be different depending on
how the device is configured and also depending on the device revision value.
Table 537: MII Register Summary
Register Description Default
1(01h) MII Status register 7809h
2(02h) PHY ID High 0040h
3(03h) PHY ID Low 6XXXh
4(04h) Auto-Negotiation Advertisement Register 01E1h
5(05h) Link Partner Ability Register 0000h
6(06h) Auto-Negotiation Expansion Register 0004h
7(07h) Next Page Register 2001h
8(08h) Link Partner Next Page 0000h
9(09h) Reserved 0000h
10(0Ah) Reserved 0000h
11(0Bh) Reserved 0000h
12(0Ch) Reserved 0000h
13(0Dh) Reserved 0000h
14(0Eh) Reserved 0000h
15(0Fh) Reserved 0000h
16(10h) 100Base-X Auxiliary Control Register 0000h
17(11h) 100Base-X Auxiliary Status Register 0000h
18(12h) 100Base-X Receive Error Counter 0000h
19(12h) 100Base-X False Carrier Counter 0000h
20(14h) 100Base-X Disconnect Counter 0200h
21(15h) Reserved 0600h
22(16h) Reserved 0100h
23(17h) PTEST (Reserved) 0000h
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