Broadcom BCM5722 - Read DMA Control Registers; Read DMA Mode Register (Offset 0 X4800); Table 307: Read DMA Control Registers-BCM5722, BCM5755, BCM5755 M, BCM5756 M, BCM5757, BCM5754, BCM5787 Only; Table 308: Read DMA Control Registers-BCM5906 Only

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 311 Read DMA Control Registers Document 5722-PG101-R
READ DMA CONTROL REGISTERS
READ DMA MODE REGISTER (OFFSET 0X4800)
Table 307: Read DMA Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754,
BCM5787 Only
Offset Registers
0x4800–0x4803 Read DMA Mode
0x4804–0x4807 Read DMA Status
0x4808–0x4bff Reserved
Note: For the BCM5906 device only, the RDMA “debug” registers listed are all read-only. Reads to these registers
return internal state values. Do not write to the RDMA debug registers.
Table 308: Read DMA Control Registers—BCM5906 Only
Offset Registers
0x4800–0x4803 Read DMA Mode
0x4804–0x4807 Read DMA Status
0x4808–0x480b Reserved
0x480c–0x4b0f RDMA debug registers 1
0x4810–0x481f Reserved
0x4820–0x4823 RDMA debug registers 2
0x4824–0x4827 Reserved
0x4828–0x484b RDMA debug registers 3–10
0x484c–0x4bff Reserved
Table 309: Read DMA Mode Register (Offset 0x4800)
Bit Field Description Init Access
31:29 Reserved – 0 RO
28 Hardware IPv6 Post-DMA Enable
(BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
Enable hardware LSO post-DMA processing for IPv6
Packets.
0R/W
Reserved (other devices) – 0 RO
27 Hardware IPv4 Post-DMA Enable Enable hardware LSO post-DMA processing for IPv4
Packets.
0R/W
26 Post-DMA Debug Enable When this bit is set, the Send Data Completion state
machine will be halted if the Post-DMA bit of the Send BD
is set.
0R/W