BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 257 Ethernet MAC Control Registers Document 5722-PG101-R
RECEIVE RULES CONTROL REGISTERS (OFFSET RULE N: 0X480 + 8*N)
The BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5787, BCM5787M, BCM5754, and BCM5754M MACs
implement eight receive rules (N = 0 to 7) only.
Note: Receive Rules Control Registers do not apply to the BCM5906 device.
Table 210: Receive Rules Control Register (Offset 0x480)
Bit Field Description Init Access
31 Enable Corresponding Rule is enabled when set. 0 R/W
30 And With Next This rule and next must both be true to match. The class
fields must be the same. A disabled next rule is considered
true. Processor activation bits are specified in the first rule
in a series.
0R/W
29 Activate Processor 1 If the rule matches, the processor is activated in the queue
descriptor for the Receive Queue Placement state
machine.
0R/W
28:27 Reserved – 00 RO
26 Mask If set, specifies that the value/mask field is split into a 16-
bit value and 16-bit mask instead of a 32-bit value.
0R/W
25 Discard Discard Frame if it matches the rule. 0 R/W
24 Map Use the masked value and map it to the class. 0 R/W
17:16 Comparison Operator Specifies how to determine the match:
• 00 = Equal.
• 01 = Not equal.
• 10 = Greater than.
• 11 = Less than.
00 R/W
15:13 Header Type Specifies which header the offset is for:
• 000 = Start of Frame (always valid).
• 001 = Start of IP Header (if present).
• 010 = Start of TCP Header (if present).
• 011 = Start of UDP Header (if present).
• 100 = Start of Data (always valid, context sensitive).
000 R/W
12:8 Class The class this frame is placed into if the rule matches. 0–16
where 0 means discard. The number of valid classes is the
Number of Active Queues divided by the Number of
Interrupt Distribution Groups. Ring 1 has the highest
priority and ring 16 has the lowest priority.
0R/W
7:0 Offset Number of bytes offset specified by the header type. 0 R/W
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