Broadcom BCM5722 - Table 126: Miscellaneous Host Control Register (Offset 0 X68)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Broadcom Vendor-Specific Capabilities Page 204
MISCELLANEOUS HOST CONTROL REGISTER (OFFSET 0X68)
The Miscellaneous Host Control register is used to control various functions within the device normally controllable from the
PCI-based host. Each bit has a separate function from any other bit in this register.
Note: See “Revision Levels” on page 8. Also see the latest errata documentation for any known errata related
to ASIC revision string information.
Table 126: Miscellaneous Host Control Register (Offset 0x68)
Bit Field Description Init Access
31:16 ASIC Revision ASIC revision string (see “Revision Levels” on page 8). See “Revision
Levels” on
page 8.
RO
15 Enable TLP Minor Error
Tolerance
Set this bit to enable TLP minor error tolerance (ATTR/TC/
LOCK command).
0R/W
14 Log Header Overflow Set this bit to enable log header due to overflow. 0 R/W
13 Boundary Check Set this bit to enable crossing 4-KB boundary check. 0 R/W
12 Byte-Enable Rule Check Set this bit to enable the byte-enable rule check. 0 R/W
11 Interrupt Check Set this bit to enable the interrupt check. 0 R/W
10 RCB Check Set this bit to enable RCB check. 0 R/W
9 Enable Tagged Status
Mode
When set, a unique eight-bit tag value will be inserted into
the Status Block Status Tag (see “Status Block” on
page 53).
0R/W
8 Mask_Interrupt_Mode When set, the INTA
signal is masked (de-asserted) at the
chip's pin. However, the internal interrupt state (host
coalescing event) will not be cleared.
0R/W
7 Enable Indirect Access Set bit to enable indirect addressing mode. 0 R/W
6 Enable Register Word
Swap
Set bit to enable word swapping when accessing registers
through the PCI target interface.
0R/W
5 Enable Clock Control
Register read/write
capability
Set bit to enable Clock Control Register read/write
capability, otherwise, the Clock Control Register is read
only (see “PCI Clock Control Register (Offset 0x74)” on
page 207).
0R/W
4 Enable PCI State Register
read/write capability
Set bit to enable PCI State Register read/write capability,
otherwise, the PCI State Register is read only (see “PCI
State Register (Offset 0x70)” on page 206).
0R/W
3 Enable Endian Word Swap Set bit to enable endian word swapping when accessing
through PCI Target interface.
0R/W
2 Enable Endian Byte Swap Set bit to enable endian byte swapping when accessing
through PCI Target interface.
0R/W
1 Mask PCI Interrupt Output Setting this bit will mask (i.e., prevent) future interrupt
events from causing INTA
to assert as long as this bit is
set. Setting this bit will not clear or de-assert the internal
interrupt state, nor will it de-assert the external interrupt
state on INTA
. In other words, setting this bit does not
disable the interrupt line because INTA
will stay asserted
if it was already asserted. However, if INTA
is not already
asserted when this bit is set, INTA
will not be asserted if
interrupt-causing event occurs later while this bit is still set.
In that scenario, the interrupt will not be presented to INTA
until this bit is cleared.
0R/W