Broadcom BCM5722 - Table 466: Phy;Link Training N_FTS (Offset 0 X7 E14); Table 467: PHY Attention Register (Offset 0 X7 E18)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 407 PCIe Registers Document 5722-PG101-R
PHY/LINK TRAINING N_FTS (OFFSET 0X7E14)
PHY ATTENTION REGISTER (OFFSET 0X7E18)
Table 466: PHY/Link Training N_FTS (Offset 0x7E14)
Bit Field Description Init Access
31:16 Reserved – 0 RO
Increase_TX_L0s_exit
(BCM5906 only)
Add programmable register to increase tx L0s exit
latency. This may be used to offset the extended tx idle/
active time in the LP version of the SerDes Analog.
0R/W
Reserved (all others) — 0 RO
15:8 Inbound N_FTS Inbound Maximum number of FTS ordered sets to be
sent when transitioning from L0s to L0 to achieve bit and
framing synchronization.
0xFF RO
7:0 Outbound N_FTS Outbound Maximum number of FTS ordered sets to be
sent when transitioning from L0s to L0 to achieve bit and
framing synchronization.
0x40 R/W
Table 467: PHY Attention Register (Offset 0x7E18)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7 Hot reset Hot reset event. Set by hot reset and cleared by explicitly
writing 1.
0W2C
6 Link down Link down event. When link status transitions from up to
down, this event bit will be set.
0W2C
5 Training error LTSSM training error. 0 W2C
4 Buffer overrun Receive elastic buffer overrun. 0 W2C
3 Buffer underrun Receive elastic buffer underrun. 0 W2C
2 Receive framing error Receive framing error. Set when receive framing error
count exceeds its threshold.
0W2C
1 Receive disparity error Receive 8b/10b running disparity error. Set when 8b10b
disparity count exceeds its threshold.
0W2C
0 Receive code error Receive 8b/10b code error. Set when 8b/10b error count
exceeds its threshold.
0W2C