Broadcom BCM5722 - Table 106: Expansion ROM Base Address Register (Offset 0 X30); Table 107: Capabilities Pointer Register (Offset 0 X34); Table 108: Interrupt Line Register (Offset 0 X3 C)

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BCM5722 Programmer’s Guide

10/15/07

Broadcom Corporation

Page 195 PCI Configuration Registers Document 5722-PG101-R

EXPANSION ROM BASE ADDRESS REGISTER (OFFSET 0X30)

The 32-bit Expansion ROM Base Address register is used to establish the location of Expansion ROM region within the

device’s memory space. This ROM region is used for PXE support. The system software can determine how much address

space the device requires by writing a value of all 1’s to the address portion of the register and then reading the value back.

The device will return 0’s in all don’t-care bits, effectively specifying the size and alignment requirements. The amount of

address space a device requests must not be greater than 16 MB.

CAPABILITIES POINTER REGISTER (OFFSET 0X34)

The 8-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list of new capabilities. The

capabilities are PCI Power Management, Vital Product Data (VPD), Message Signaled Interrupts (MSI), and PCIe (PCIe).

INTERRUPT LINE REGISTER (OFFSET 0X3C)

The 8-bit Interrupt Line register is used to communicate interrupt line routing information. This field is set after configuration

by the host and later used by any driver which needs to know which physical interrupt on the system interrupt controller is

assigned to this device. The device supports any value in this field.

INTERRUPT PIN REGISTER (OFFSET 0X3D)

The 8-bit Interrupt Pin register is used to indicate which interrupt pin the device uses. This is hardwired for INTA (0x01).

Table 106: Expansion ROM Base Address Register (Offset 0x30)

Bit Field Description Init Access

31:11 ROM Base Address Address bits. X RO

a. RO unless Expansion ROM Enable bit is enabled.

10:1 Reserved – 000h RO

0 Expansion ROM

Enable

Set to a 1 to enable the use of this ROM region (firmware

only).

0Config-RO

Firmware-R/W

Table 107: Capabilities Pointer Register (Offset 0x34)

Bit Field Description Init Access

7:0 Capabilities Pointer Points to a linked list of new PCI capabilities. 48h RO

Table 108: Interrupt Line Register (Offset 0x3C)

Bit Field Description Init Access

7:0 Interrupt Line Identifies interrupt routing information. 0 R/W