Broadcom BCM5722 - Table 500: Expansion Register 03 H: Serdes Control

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 436
Expansion Interrupt Status
These bits corresponds to the Expansion Interrupt Status bits.
Transmit CRC Error (Copper Only)
Bit 0 = 1 indicates that a transmit CRC error occurred since the register was last read, otherwise, it returns a 0.
EXPANSION REGISTER 03H: SERDES CONTROL
The following expansion registers are enabled by writing to “Expansion Register Access Register (PHY_ADDR = 0x1,
Reg_Addr = 17h)” on page 434 bits [11:0] = F03h, and read/write access is through register 15h.
Clock Pad Disable
This bit disables SGMII clock pads SCLK±. The default is to have the SCLK± enabled.
Table 500: Expansion register 03h: SerDes Control
Bit Field Description Init Access
15 Reserved Write as 0, ignore on read. 0 RO
14:2 Reserved Write as 1031h, ignore on read. 1031h R/W
1 Clock Pad Disable
• 1 = Disable SGMII clock pads SCLK±
• 0 = Enable SGMII clock pads SCLK±
0R/W
0 Reserved Write as 0, ignore on read. 0 RO