Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Broadcom Vendor-Specific Capabilities Page 206
PCI STATE REGISTER (OFFSET 0X70)
The PCI State register is used to control several functions within the device associated with the PCI interface.
0
Note: The Enable PCI State Register Read/Write Capability bit of the Miscellaneous Host Control register must
be enabled to write the PCI State register from the PCI configuration cycle (see “Miscellaneous Host Control
Register (Offset 0x68)” on page 204).
Table 128: PCI State Register (Offset 0x70)
Bit Field Description Init Access
31:16 Reserved – 0 RO
15 Config Retry When asserted, forces all config access to be retried. 1 R/W
14 Reserved – 0 RO
13 Retry Same DMA (other
devices)
When set, prevents internal arbitration logic from switching to
the other DMA engine after a retry cycle.
0R/W
12 3.3VAux Present This bit reads as 1 when the 3.3V auxiliary power source is
present.
0RO
11:9 Max PCI Target Retry Indicates the number of PCI clock cycles before Retry occurs,
in multiple of 8. At reset, this field is set to 001.
001 RO
a
a. Bit-enabled R/W through PCI configuration space.
8 Flat View Asserted if the Base Address Register presents a 32 MB PCI
Address Map Flat View, otherwise, indicates a 64 KB PCI
Address Map Standard View.
0RO
a
7 VPD Available This bit reads as 1 if the VPD region of the NVRAM can be
accessed by the host.
0RO
6 PCI Expansion ROM Retry Force PCI Retry for accesses to Expansion ROM region, if
enabled.
0RO
a
5 PCI Expansion ROM
Desired
Enable PCI ROM Base Address Register to be visible to the
PCI host.
0RO
a
4:2 Reserved – 0 RO
1 PCI INT state Reflect the state of PCI INTA
1RO
0 Reserved – 0 RO
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