Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Ethernet MAC Control Registers Page 252
MI MODE REGISTER (OFFSET 0X454)
This register controls autopolling on the management interface. Auto control mode sets the link state in the transmit state
register.
AUTOPOLLING STATUS REGISTER (OFFSET 0X458)
This register contains status of autopolling the management interface.
Table 202: MI Mode Register (Offset 0x454)
Bit Field Description Init Access
31:21 Reserved – 0 RO
20:16 MI Clock Count Counter to divide CORE_CLK (i.e., 66 MHz) to generate
the MI clock. The formula is:
MI Clock = CORE_CLK/2/(MI Clock Count + 1)
0ch R/W
15:10 Reserved – 0 RO
9:5 PHY Address This field specifies the PHY address. 00001 R/W
4 Port Polling Set to enable autopolling of the transceiver link information
from the MII Management interface. If cleared, the device
will obtain the link status information from the state of the
LNKRDY input signal.
0R/W
3:2 Reserved – 0 RO
1 Use Short Preamble Use short preamble while polling, if set. 0 R/W
0 Reserved – 0 RO
Table 203: Autopolling Status Register (Offset 0x458)
Bit Field Description Init Access
31:1 Reserved Always 0. 0 RO
0 Auto-polling Error Indicates an autopolling error occurred if set. 0 W2C
To Next Page
Loading...