Broadcom BCM5722 - Table 468: PHY Attention Mask Register (Offset 0 X7 E1 C); Table 469: PHY Receive Error Counter (Offset 0 X7 E20); Table 470: PHY Receive Framing Error Counter (Offset 0 X7 E24)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 408
PHY ATTENTION MASK REGISTER (OFFSET 0X7E1C)
PHY RECEIVE ERROR COUNTER (OFFSET 0X7E20)
PHY RECEIVE FRAMING ERROR COUNTER (OFFSET 0X7E24)
Table 468: PHY Attention Mask Register (Offset 0x7E1C)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7 Hot reset mask Hot reset event mask bit. 0 R/W
6 Link down mask Link down event mask bit. 0 R/W
5 Training error mask LTSSM training error mask bit. 0 R/W
4 Buffer overrun mask Receive elastic buffer overrun mask bit. 0 R/W
3 Buffer underrun mask Receive elastic buffer underrun mask bit. 0 R/W
2 Receive frame error
mask
Receive frame error mask bit. 0 R/W
1 Receive disparity error
mask
Receive 8b/10b running disparity error mask bit. 0 R/W
0 Receive code error
mask
Receive 8b/10b code error mask bit. 0 R/W
Table 469: PHY Receive Error Counter (Offset 0x7E20)
Bit Field Description Init Access
31:16 Disparity error count Receive 8b/10b running disparity error count. 0 R/W
15:0 Code error count Receive 8b/10b coding error count. 0 R/W
Table 470: PHY Receive Framing Error Counter (Offset 0x7E24)
Bit Field Description Init Access
31:16 Reserved – 0 RO
15:0 Framing error count Receive framing error count. 0 RO