Broadcom BCM5722 - Flow-Through Queues; FTQ Reset Register (Offset 0 X5 C00); Table 330: Flow-Through Queues Registers; Table 331: FTQ Reset Register (Offset 0 X5 C00)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Flow-Through Queues Page 326
FLOW-THROUGH QUEUES
FTQ RESET REGISTER (OFFSET 0X5C00)
Table 330: Flow-Through Queues Registers
Offset Registers
0x5C00–0xC403 FTQ Reset Register
0x5C04–0x5CB7 Reserved
0x5CB8–0x5CBB MAC TX FIFO Enqueue Register
0x5CBC–0x5CC7 Reserved
0x5CC8–0x5CCB RXMBUF Cluster Free Enqueue Register (Reserved BCM5906 only)
0x5CCC–0x5CFB Reserved
0x5CFC–0x5CFF RDIQ FTQ Write/Peek Register
0x5D00–0x5FFF Reserved
Table 331: FTQ Reset Register (Offset 0x5C00)
Bit Field Description Init Access
31:17 Reserved – 0 RO
16 Reset Receive Data
Completion FTQ
Set this bit to reset the Receive Data Completion flow
through queue. When set to 0, this flow through queue is
ready for use. This bit is self-clearing.
R/W
15 Reserved – 0 RO
14 Reset Receive List
Placement FTQ
Set this bit to reset the Receive List. This bit is self-clearing
placement flow through queue. When set to 0, this flow
through queue is ready to use. This bit is self-clearing.
R/W
13 Reset Receive BD
Complete FTQ
Set this bit to reset the Receive BD Complete flow through
queue. When set to 0, this flow through queue is ready for
use. This bit is self-clearing.
R/W
12 Reserved – 0 RO
11 Reset MAC TX FTQ Set this bit to reset the MAC TX flow through queue. When
set to 0, this flow through queue is ready for use. This bit
is self-clearing.
R/W
10 Reset Host Coalescing
FTQ
Set this bit to reset the Host Coalescing flow through
queue. When set to 0, this flow through queue is ready for
use. This bit is self-clearing.
R/W
9 Reset Send Data
Completion FTQ
Set this bit to reset the Send Data Completion flow through
queue. When set to 0, this flow through queue is ready for
use. This bit is self-clearing.
R/W
8 Reserved – 0 RO
7 Reset DMA High Priority
Write FTQ
Set this bit to reset the DMA High Priority Write flow
through queue. When set to 0, this flow through queue is
ready for use. This bit is self-clearing.
R/W
6 Reset DMA Write FTQ Set this bit to reset the DMA Write flow through queue.
When set to 0, this flow through queue is ready for use.
This bit is self-clearing.
R/W
5 Reserved – 0 RO