BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 273 TCP Segmentation Control Registers Document 5722-PG101-R
TCP SEGMENTATION CONTROL REGISTERS
LOWER HOST ADDRESS REGISTER FOR TCP SEGMENTATION (OFFSET 0XCE0)
UPPER HOST ADDRESS REGISTER FOR TCP SEGMENTATION (OFFSET 0XCE4)
LENGTH/OFFSET REGISTER FOR TCP SEGMENTATION (OFFSET 0XCE8)
Table 235: TCP Segmentation Control Registers
Offset Registers
0x0ce0–0x0ce3 Lower Host Address Register for TCP Segmentation
0x0ce4–0x0ce7 Upper Host Address Register for TCP Segmentation
0x0ce8–0x0ceb Length/Offset Register for TCP Segmentation
0x0cec–0x0cef DMA Flags Register for TCP Segmentation
0x0cf0–0x0cf3 VLAN Tag Register for TCP Segmentation
0x0cf4–0x0cf7 Pre-DMA Command Exchange Register for TCP Segmentation
0xcf8–0xfff Reserved
Table 236: Lower Host Address Register for TCP Segmentation (Offset 0xCE0)
Bit Field Description Init Access
31:0 Specifies the lower 32 bits of the starting address in host
memory where the transmit data buffer resides.
0R/W
Table 237: Upper Host Address Register for TCP Segmentation (Offset 0xCE4)
Bit Field Description Init Access
31:0 Specifies the upper 32 bits of the starting address in host
memory where the transmit data buffer resides.
0R/W
Table 238: Length/Offset Register for TCP Segmentation (Offset 0xCE8)
Bit Field Description Init Access
31:23 Reserved – 0 RO
22:16 MBUF offset MBUF offset. It specifies the offset of the first TXMBUF at
where the DMA starts putting data. The valid value is
between 48 and 128.
0R/W
15:0 Specifies the length of data to be transmitted. Although
firmware can specify up to 64 KB, it should not attempt to
program more than 8 KB because it would exceed the
size of TXMBUF.
0R/W