Broadcom BCM5722 - Table 440: Data Link Status Register (Offset 0 X7 D04)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 397 PCIe Registers Document 5722-PG101-R
DATA LINK STATUS REGISTER (OFFSET 0X7D04)
Table 440: Data Link Status Register (Offset 0x7D04)
Bit Field Description Init Access
31:26 Reserved Write as 0, ignore when read. 0 RO
25:23 PHY Link State
a
a. These bits are for debug only—they will always return 0 (except Data Link Up = 1) when read through the PCIe interface.
Current physical layer power state.
• 000 = L0
• 001 = L0s
• 010 = L1
• 011 = L2
• 100 = others
100 RO
22:19 Power Management
Statea
Current state of power management substate machine (see test doc
for state mapping).
1000 RO
18–17 Power Management
Sub-Statea
Current state of power management substate machine (see test doc
for state mapping).
00 RO
16 Data Link Upa Data link is up (VC0 initialized). 0 RO
15:10 Reserved Write as 0, ignore when read. 0 RO
9 Flow Control Update
Timeout
Flow control update timeout error detected (DLLP receive timer
expired without receiving valid DLLP).
0RO/CR
8 Flow Control Receive
Overflow
Flow control receive overflow error detected. 0 RO/CR
7 Flow Control Protocol
Error
Flow control protocol error detected. 0 RO/CR
6 Data Link Protocol
Error
Data link protocol error detected (pos or neg acknowledgement
received with invalid TLP sequence number).
0RO/CR
5 Replay Rollover Replay counter rolled over (four consecutive retries without a positive
acknowledgement received).
0RO/CR
4 Replay Timeout Replay timer expired (no ACK received within specified time). 0 RO/CR
3 NAK Received Negative acknowledgement DLLP was received. 0 RO/CR
2 DLLP Error Data link layer packet error detected. 0 RO/CR
1 Bad TLP Sequence
Number
TLP received with invalid sequence number. 0 RO/CR
0 TLP Error Transaction layer packet error detected (packet failed data link layer
error checks).
0RO/CR