Broadcom BCM5722 - Table 170: Device Serial no Enhanced Capability Header Register (Offset 0 X160); Table 171: Device Serial no Lower DW Register (Offset 0 X164)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe-Enhanced Capabilities Page 230
DEVICE SERIAL NO ENHANCED CAPABILITY HEADER REGISTER (OFFSET 0X160)
DEVICE SERIAL NO LOWER DW REGISTER (OFFSET 0X164)
Table 170: Device Serial No Enhanced Capability Header Register (Offset 0x160)
Bit Field Description Init Access
31:20 Next Capability Offset 0x16C when bit-6 of 0x7C04 is set to1
0x0 when bit-6 of 0x7C04 is set to 0
RO
Reserved (BCM5906 only) – – RO
19:16 Revision ID 0x1 RO
15:0 PCIe Capability ID PCIe Device Serial
Number Capability
ID
0x0003 RO
Table 171: Device Serial No Lower DW Register (Offset 0x164)
Bit Field Description Init Access
31:24 reserved By default this field is 0xFE after reset.
If bit 23 of register offset 0x7c04 is 1, this field is
programmable using PCI memory write cycles or the
indirect register access method via PCI
configuration writes to PCI configuration registers
0x78 and 0x80. If bit 23 of 0x7c04 is 0, this field is
read-only.
0xFE Config-RO
Memory-RW
23:0 Lower MAC Address This field is 0xFFFFFF after reset.
If bit 23 of register offset 0x7c04 is 1, this field is
programmable using PCI memory write cycle or
indirect register access method via PCI
configuration write cycles to PCI configuration
registers 0x78 and 0x80.
If bit 23 of register offset 0x7c04 is 0, this register is
not writable. In addition, the content of the MAC
Address register is copied into this register
automatically.
Bootcode sets bit 23 of 0x7c04 after it has
programmed the MAC address into registers 0x410
and 0x414. This ensures that when the driver
changes the value at offset 0x410 or 0x414, the
content of this register remains unchanged.
0xFFFFFF Config-RO
Memory-RW