Broadcom BCM5722 - Table 367: Energy_Det Control Register (Offset: 0 X68 B0)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 353 Wake-on-LAN Registers Document 5722-PG101-R
ENERGY_DET CONTROL REGISTER (OFFSET: 0X68B0)
This register applicable to BCM5906 only.
16 PERST Override This bit is used to override the PERSTN so that internal
CPU can access the PCIe register when Perstn is
asserted
• 1 = Override Perstn Reset
• 0 = No Override
Hard_
Reset
0R/W
15:0 Reserved – 0 RO
Table 367: Energy_Det Control Register (Offset: 0X68B0)
Bit Field Description Init Access
31 energy_det_apd status energy_det signal after MAC digital debouncer RO
30 energy_det_hw energy_det_hw signal after new hardware debounce logic RO
29 energy_det_system Final system level energy_det signal to energy_det output RO
28 Reserved Reserved 0 R/W
27 energy_det_apd state energy_det_apd state before PCIE reset RO
26:18 Reserved Reserved 0 R/W
17 Disable clock switching
logic based on link
status
0: Switch to ck25 from MII clocks if there is no link and no MII
clock running.
1: Switch to ck25 from MII clocks if no MII clocks running.
0 R/W
16 Disable MII clock
switching logic
0: Switch to ck25 from MII clocks based on bit 17 setting.
1: Do not switch MII clock to ck25.
0R/W
15:13 Reserved Reserved 0 R/W
12 Select_HW_Energy_D
et
0: Select Combination of Software Force_Energy_Det and
Output of Debounce Logic to generate System Energy_Det
based on Bit[11].
1: Select Output of Debounce Logic to Generate System
Energy_Det.
1R/W
11 Select_SW_Energy_D
et
0: Generate System Energy_Det by Oring the Software
Force_Energy_Det and Output of Debounce Logic.
1: Select Force_Energy_Det Control Bit to Generate System
Energy_Det.
0R/W
10 Force_Energy_Det 0: Drive Energy_Det low if enabled by Bit[12:11]
1: Drive Energy_Det high if enabled by Bit[12:11]
1R/W
9 Disable debounce low 0: Debounce low logic enabled
1: Debounce low logic disabled
0R/W
8 Enable debounce high 0: Disable Debounce high function.
1: Enable Debounce high function.
1R/W
7:6 Debounce_high_ctrl[1:
0]
00: Debounce engery_det high for another 5 sec
01: Debounce engery_det high for another 10 sec
10: Debounce engery_det high for another 15 sec
11: Debounce engery_det high for another 20 sec
01 R/W
Table 366: Power Management Debug Register (Offset: 0x68A4) (Cont.)
Bit Field Description Reset Init Access