Broadcom BCM5722 - Host Coalescing Mode Register (Offset 0 X3 C00)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Host Coalescing Control Registers Page 294
HOST COALESCING MODE REGISTER (OFFSET 0X3C00)
Table 284: Host Coalescing Mode Register (Offset 0x3C00)
Bit Field Description Init Access
31:13 Reserved – 0 R/W
12 No Interrupt on Force
Update
When set, writing the Coalesce Now bit will cause a
status block update without a corresponding interrupt
event.
R/W
11 No Interrupt on DMAD
Force
When set, the COAL_NOW bit of the buffer descriptor
may be set to force a status block update without a
corresponding interrupt (see “Send Buffer Descriptors”
on page 46).
R/W
10 Clear Ticks Mode on
TX
When set, the TX Host Coalescing Tick counter initializes
to the idle state and begins counting only after a transmit
BD event is detected.
R/W
Reserved (BCM5906
Only)
–0RO
9 Clear Ticks Mode on
RX
When set, the RX Host Coalescing Tick counter
initializes to the idle state and begins counting only after
a receive BD event is detected.
R/W
8–7 Status Block Size Status Block Size for partial status block updates (see
“Status Block” on page 53):
• 00 = Full status block
• 01 = 64 byte
• 10 = 32 byte
• 11 = Undefined
R/W
Reserved (BCM5906
Only)
–0R/W
6:4 MSI Bits The least significant MSI 16-bit word is overwritten by
these bits. Defaults to 0.
R/W
3 Coalesce Now If set, Host Coalescing updates the Status Block
immediately and sends an interrupt to host. This is a self-
clearing bit. (For debug purpose only.)
R/W
2 Attn_Enable When this bit is set to 1, an internal attention is generated
when an error occurs.
R/W
1 Enable This bit controls whether the Host Coalescing state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains one when read.
R/W
0 Reset When this bit is set to 1, the Host Coalescing state
machine is reset. This is a self-clearing bit.
R/W