BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 347 Wake-on-LAN Registers Document 5722-PG101-R
MISCELLANEOUS CABLESENSE CONTROL REGISTER (OFFSET: 0X6890)
Table 360: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—
BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
Bit Field Description Init Access
31 EEPROM Clock
Divider fix disable
(BCM5722,
BCM5755,
BCM5755M,
BCM5756M,
BCM5757 only)
Disable EEPROM Clock Divider fix
This bit is reset by hard_reset
0R/W
Reserved (other
devices)
–0RO
30:29 Reserved 0 RO
27 CLKREQ# Disable
(BCM5722,
BCM5755,
BCM5755M,
BCM5756M,
BCM5757 only)
CLKREQ# disable
This bit is reset by hard_reset
0R/W
Reserved – 0 RO
26 Energy_det_sel
(BCM5722,
BCM5755,
BCM5755M,
BCM5756M,
BCM5757 only)
1: Select energy_det_raw and generate energy_det output using
MAC digital debouncer.
0: Select energy_det_apd to generate energy_det output.
The energy_det output pin is shared with GPIO3 in Baxter. Stanford
has dedicated output pin for this signal.
This bit is reset by hard_reset only and formerly called gpio3. For
BCM5756M only, this bit is reset by POR only.
0R/W
Reserved – 0 RO
25 CableSense_enable Define how the LOW_POWER_MODE behaves.
1: CableSense Mode Enable
0: Normal LOWER_POWER_MODE
This bit is reset by hard_reset only, and its original name is
Super
Airplane Mode
. For BCM5756M only, this bit is reset by POR only.
0R/W
24:0 Reserved – 0 RO
Table 361: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—BCM5906 Only
Bit Field Description Init Access
31 Reserved – 0 R/W
30 Magic power down If driver or system software sets this bit to “1”, VCPU powers down
the device.
0R/W
29 WOL_disable For the driver to disable VCPU WOL setup, this bit should be set. This
bit is cleared by hard reset.
0R/W
28 CLKREQ# Pin
Disable(Apply on
BCM5906/BCM5906M
A2 and after)
1: External CLKREQ# pin is hardwired to “0”; internal clkreq signal
behaves the same.
0: External CLKREQ# pin behaves the same as internal clkreq signal
This bit is reset by hard_reset
.
0R/W