Broadcom BCM5722 - Table 356: Wake-On-LAN Registers; Table 357: WOL Mode Register (Offset 0 X6880); Table 358: WOL Config Register (Offset 0 X6884)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 345 Wake-on-LAN Registers Document 5722-PG101-R
WAKE-ON-LAN REGISTERS
WOL MODE REGISTER (OFFSET 0X6880)
WOL CONFIG REGISTER (OFFSET 0X6884)
Note: The Wake-on-LAN registers do not apply to the BCM5906 device.
Table 356: Wake-on-LAN Registers
Field Description
0x6880–0x6883 WOL Mode Register
0x6884–0x6887 WOL Config Register
0x6888–0x688B WOL State Machine Status Register
0x688C–0x688F Reserved
Table 357: WOL Mode Register (Offset 0x6880)
Bit Field Description Init Access
31:5 Reserved – 0 R/W
4 WOL_PWR_CTRL Use to manually switch the power FETs. 0 R/W
3:2 WOL_PWR_SW_PRO
G
Control the WOL voltage comparator threshold (100 mV
increment).
0R/W
1 Enable This bit controls whether the WOL is active or not.
• When set to 0, it completes the current operation and
cleanly halts.
• Until it is completely halted, it remains one when read.
0R/W
0 Reset When set, the entire WOL state machines are reset. This
bit is self-clearing.
0R/W
Table 358: WOL Config Register (Offset 0x6884)
Bit Field Description Init Access
31:17 Reserved When set to 1, it indicates the main power is available. 0 R/W
16 SC_sim_mode When set to 1, it accelerate the simulations. It waits only
0.5 µs. When set to 0, it is normal operation.
0R/W
15:14 SC_delay_cfg When set to 00, it accelerates the simulations for
slow_clock_ctl.
• 00 = waits 10 µs.
• 01 = waits 35 µs.
• 10 = waits 50 µs.
• 11 = waits 65 µs.
0R/W
13 SD_sim_mode
• 0 = normal operation mode. The total delay is
SD_delay_cfg x1000.
• 1 = waits 0.5 µs.
0R/W