BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 167 Wake on LAN Mode/Low-Power Document 5722-PG101-R
REGISTER QUICK CROSS REFERENCE
Integrated PHYs
Table 83 lists the WOL mode control registers in the integrated PHYs.
Table 83: PHY WOL Mode Control Registers
MDI Register Bit(s) Name Description Cross Reference
Auto_Negotation
_Advertisement
10_BASE_TX_Half_
Duplex
Advertise to link partner that local PHY is
capable of 10 Mbps half-duplex
operation.
“Auto-Negotiation Advertisement
Register (PHY_Addr = 0x1,
Reg_Addr = 04h)” on page 419.
10_BASE_TX_Full_
Duplex
Advertise to link partner that local PHY is
capable of 10 Mbps full-duplex
operation.
100_BASE_TX_Half_
Duplex
Advertise to link partner that local PHY is
capable of 100 Mbps half-duplex
operation.
100_BASE_TX_Full_
Duplex
Advertise to link partner that local PHY is
capable of 100 Mbps full-duplex
operation.
1000BASE-
T_Control
1000_BASE_TX_Half_D
uplex
Advertise to link partner that local PHY is
capable of 1000 Mbps half-duplex
operation.
“1000BASE-T Control Register
(PHY_Addr = 0x1, Reg_Addr =
09h)” on page 425.
1000_BASE_TX_Full_D
uplex
Advertise to link partner that local PHY is
capable of 1000 Mbps full-duplex
operation.
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