Broadcom BCM5722 - Table 111: Power Management Capability Register (Offset 0 X48); Table 112: PM Next Capabilities Pointer Register (Offset 0 X49); Table 113: Power Management Capabilities Register (Offset 0 X4 A)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 197 PCI Power Management Capabilities Document 5722-PG101-R
PCI POWER MANAGEMENT CAPABILITIES
Devices that support PCI Power Management must support a block of registers that is part of the Capabilities List in PCI
Configuration Space. The PCI Power Management Register Block is located at offset 0x48. The device supports the
following PCI Power Management registers.
POWER MANAGEMENT CAPABILITY ID REGISTER (OFFSET 0X48)
This 8-bit register identifies this item in the Capabilities List as a PCI Power Management register set.
PM NEXT CAPABILITIES POINTER REGISTER (OFFSET 0X49)
This register points to the next item in the Capabilities List.
POWER MANAGEMENT CAPABILITIES REGISTER (OFFSET 0X4A)
Table 111: Power Management Capability Register (Offset 0x48)
Bit Field Description Init Access
7:0 PM Capability ID Identifies this item as Power Management capabilities. 01h RO
Table 112: PM Next Capabilities Pointer Register (Offset 0x49)
Bit Field Description Init Access
7:0 PM Next Capabilities Points to the next capabilities block which is for Vital
Product Data (VPD).
50h RO
Table 113: Power Management Capabilities Register (Offset 0x4A)
Bit Field Description Init Access
15:11 PME Support Indicates the power states in which the device may assert
PME
. A 0 for any bit indicates that the device is not capable
of asserting the PME
pin signal while in that power state.
• Bit 11 = PME can be asserted from D0. Default is 0.
• Bit 12 = PME can be asserted from D1. Default is 0.
• Bit 13 = PME can be asserted from D2. Default is 0.
• Bit 14 = PME can be asserted from D3Hot. Default is 1.
• Bit 15 = PME can be asserted from D3Cold. Default
depends on the presence of an Aux power supply.
Auxiliary power is detected by the presence of power on
the VAUX_PRSNT signal pin.
01000 if Aux
is not
present
11000 if Aux
present
RO
10 D2 Support Indicates whether the device supports the D2 power
management state. This device does not support D2, so this
bit is hardwired to 0.
0RO
9 D1 Support Indicates whether the device supports the D1 power
management state. This device does not support D1, so this
bit is hardwired to 0.
0RO