Broadcom BCM5722 - Table 278: Receive BD Completion Control Registers; Table 279: Receive BD Completion Mode Register (Offset 0 X3000); Table 280: Receive BD Completion Status Register (Offset 0 X3004); Table 281: NIC Standard Receive BD Producer Index (Offset 0 X300 C)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 291 Receive BD Completion Control Registers Document 5722-PG101-R
RECEIVE BD COMPLETION CONTROL REGISTERS
RECEIVE BD COMPLETION MODE REGISTER (OFFSET 0X3000)
RECEIVE BD COMPLETION STATUS REGISTER (OFFSET 0X3004)
NIC STANDARD RECEIVE BD PRODUCER INDEX REGISTER (OFFSET 0X300C)
Table 278: Receive BD Completion Control Registers
Offset Registers
0x3000–0x3003 Receive BD Completion Mode
0x3004–0x3007 Receive BD Completion Status
0x3008–0x300b Reserved
0x300c–0x300f NIC Standard Receive BD Producer Index
0x3010–0x37ff Reserved
Table 279: Receive BD Completion Mode Register (Offset 0x3000)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Attn_Enable When this bit is set to 1, an internal attention is generated
when an error occurs.
R/W
1 Enable This bit controls whether the Receive BD Completion state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains one when read.
1R/W
0 Reset When this bit is set to 1, the Receive BD Completion state
machine is reset. This is a self-clearing bit.
0R/W
Table 280: Receive BD Completion Status Register (Offset 0x3004)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Error Receive BD Completion error status. RO
1:0 Reserved – 0 RO
Table 281: NIC Standard Receive BD Producer Index (Offset 0x300C)
Bit Field Description Init Access
31:9 Reserved – 0 RO
8–0 NIC Standard Receive BD
Producer Index
––R/W