Broadcom BCM5722 - Table 225: Send Data Initiator Mode Register (Offset 0 X0 C00)-BCM5722, BCM5755, BCM5755 M, BCM5756 M, BCM5757, BCM5754, BCM5787 Only; Table 226: Send Data Initiator Mode Register (Offset 0 X0 C00)-BCM590 X Only

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 269 Send Data Initiator Control Registers Document 5722-PG101-R
SEND DATA INITIATOR MODE REGISTER (OFFSET 0X0C00)—BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787, AND BCM5906 ONLY
SEND DATA INITIATOR MODE REGISTER (OFFSET 0X0C00)—BCM5907 ONLY
Table 225: Send Data Initiator Mode Register (Offset 0x0C00)—BCM5722, BCM5755, BCM5755M, BCM5756M,
BCM5757, BCM5754, BCM5787 Only
Bit Field Description Init Access
31:5 Reserved – 0 RO
4 Pre-DMA Debug Enable When this bit is set, the Send Data Initiator state machine
is halted when the pre-DMA bit of the Send BD is set.
0R/W
3 Hardware Pre-DMA Enable Enable hardware LSO pre-DMA processing 0 R/W
2 Stats Overflow Attn Enable Enable attention for statistics overflow 0 R/W
1 Enable This bit controls whether the Send Data Initiator state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains 1 when read.
1R/W
0 Reset When this bit is set to 1, the Send Data Initiator state
machine is reset. This is a self-clearing bit.
0R/W
Table 226: Send Data Initiator Mode Register (Offset 0x0C00)—BCM590X Only
Bit Field Description Init Access
31:8 Reserved – 0 RO
7 dec_1ms When set, the timer at 0xc24 is decremented by
0x100000. When done, the bit is cleared by hardware.
This bit may stay high for as long as 1 ms before it gets
cleared.
a
a. Bits 7:4 can be set simultaneously. Software must poll these bits to ensure that they are all 0's before setting any of these bits.
0R/W
6 inc_64us When set, the timer at 0xc24 is incremented by 0x10000.
When done, the bit is cleared by hardware.
a
0R/W
5 inc_4us When set, timer at 0xc24 is incremented by 0x1000.
When done, the bit is cleared by hardware.
0R/W
4 inc_512ns When set, the timer at 0xc24 is incremented by 0x100.
When done, the bit is cleared by hardware.
a
0R/W
3 Hardware Pre-DMA Enable Enable hardware LSO pre-DMA processing 0 R/W
2 Stats Overflow Attn Enable Enable attention for statistics overflow 0 R/W
1 Enable This bit controls whether the Send Data Initiator state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains 1 when read.
1R/W
0 Reset When this bit is set to 1, the Send Data Initiator state
machine is reset. This is a self-clearing bit.
0R/W