Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R ASF Support Registers Page 360
POLL ASF TIMER REGISTER (OFFSET 0X6C14)
POLL LEGACY TIMER REGISTER (OFFSET 0X6C18)
RETRANSMISSION TIMER REGISTER (OFFSET 0X6C1C)
TIME STAMP COUNTER REGISTER (OFFSET 0X6C20)
Table 374: Poll ASF Timer Register (Offset 0x6C14)
Bit Field Description Init Access
31:8 Reserved – 0 R/W
7:0 Poll timer A countdown timer which decrements at the rate of one
tick per 5 ms. When the counter reaches a value of zero,
the corresponding timeout bit is set in the ASF Control
Register (see “ASF Control Register (Offset 0x6C00)” on
page 356). The timer stops decrementing when it
reaches the zero value.
0R/W
Table 375: Poll Legacy Timer Register (Offset 0x6C18)
Bit Field Description Init Access
31:8 Reserved – 0 R/W
7:0 Poll Legacy timer A countdown timer which decrements at the rate of one
tick per 250 ms. When the counter reaches a value of
zero, the corresponding timeout bit is set in the ASF
Control Register (see “ASF Control Register (Offset
0x6C00)” on page 356). The timer stops decrementing
when it reaches the zero value.
0R/W
Table 376: Retransmission Timer Register (Offset 0x6C1C)
Bit Field Description Init Access
31:8 Reserved – 0 R/W
7:0 Poll timer A countdown timer which decrements at the rate of one
tick per second. When the counter reaches a value of
zero, the corresponding timeout bit is set in the ASF
Control Register (see “ASF Control Register (Offset
0x6C00)” on page 356). The timer stops decrementing
when it reaches the zero value.
0R/W
Table 377: Time Stamp Counter Register (Offset 0x6C20)
Bit Field Description Init Access
31: 0 Timestamp Counter A count-up timer which increments at the rate of one tick
per second. The counter starts when the Time Stamp
Counter Enable bit is set in the ASF Control register (see
“ASF Control Register (Offset 0x6C00)” on page 356).
0R/W
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