BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 343 General Control Registers Document 5722-PG101-R
RX CPU EVENT ENABLE REGISTER (OFFSET 0X684C)
Setting a bit in this register enables an interrupt to the CPU or the event.
Table 354: RX CPU Event Enable Register (Offset 0x684C)—BCM5722, BCM5755, BCM5755M, BCM5756M,
BCM5757, BCM5754, BCM5787 Only
Bit Field Description Init Access
31 Flash – 0 RO
30 VPD – 0 RO
29 Timer Reference
Reached
–0 R/W
28 ROM – 0 RO
27 HC module – 0 RO
26 RX CPU module – 0 RO
25 EMAC module – 0 RO
24 Memory Map Enable Bit Set by HW, cleared by SW. 0 R/W
23 Reserved – 0 R/W
22 High-Priority Mail Box – 0 RO
21 Low-Priority Mail Box – 0 RO
20 DMA – 0 RO
19 Reserved – 0 R/W
18–17 Reserved – 00 R/W
16 ASF Location 15 – 0 R/W
15 TPM Interrupt Enable – 0 R/W
14 ASF Location 14 – 0 R/W
13 Reserved – 0 R/W
12 ASF Location 13 – 0 R/W
11 Unused SDI – 0 R/W
10 SDC (Post TCP
segmentation)
–0 RO
9 SDI (Pre TCP
segmentation)
–0 RO
8 RDIQ FTQ (Received an
ASF)
–0 RO
7 ASF Location 12 – 0 R/W
6 Reserved – 0 R/W
5 ASF Location 11 – 0 R/W
4 Reserved – 0 R/W
3 ASF Location 10 – 0 R/W
2 Reserved – 0 R/W
1 ASF Location 9 – 0 R/W
0 ASF Location 8 – 0 R/W
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