Broadcom BCM5722 - Flow Attention Register (Offset 0 X3 C48); Receive Max Coalesced BD Count During Interrupt (Offset 0 X3 C20); Send Max Coalesced BD Count During Interrupt (Offset 0 X3 C24); Status Block Base Address Register (Offset 0 X3 C44)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 297 Host Coalescing Control Registers Document 5722-PG101-R
RECEIVE MAX COALESCED BD COUNT DURING INTERRUPT (OFFSET 0X3C20)
This register is similar to “Receive Max Coalesced BD Count (Offset 0x3C10)” on page 296, but it is used instead when the
host is considered to be in its interrupt service routine (ISR). In this case, the NIC considers the host to be in its ISR whenever
“Interrupt Mailbox 0 Register (Offset 0x200–0x207)” on page 238” for host standard and flat modes is set to a nonzero value,
or the Mask Interrupt bit is set.
SEND MAX COALESCED BD COUNT DURING INTERRUPT (OFFSET 0X3C24)
This register is similar to “Send Max Coalesced BD Count (Offset 0x3C14)” on page 296, but this register is used instead
when the host is considered to be in its ISR. In this case, the NIC considers the host to be in its ISR whenever “Interrupt
Mailbox 0 Register (Offset 0x200–0x207)” on page 238 for host standard and flat modes is set to a nonzero value, or when
the Mask Interrupt bit is set.
STATUS BLOCK HOST ADDRESS REGISTER (OFFSET 0X3C38)
This 64-bit register is in host address format and tells the NIC where to DMA the status block.
STATUS BLOCK BASE ADDRESS REGISTER (OFFSET 0X3C44)
This 32-bit register is the location of the status block structure in NIC memory.
FLOW ATTENTION REGISTER (OFFSET 0X3C48)
The Flow attention register reports attentions from the various transmit and receive state machines, flow-through queues
and the MBUF allocator. Whenever one of these blocks detects an attention situation, it sets the appropriate bit in the Flow
attention register. Refer to the state machine causing the attention to determine the exact cause. The attention bits are
cleared by writing a one to the bit (W2C). If a bit is marked as fatal, it means that the associated state machine is halted, and
that corrective action must be taken by a CPU.
Table 286: Flow Attention Register (Offset 0x3C48)
Bit Field Description Init Fatality
31 Send BD Initiator The Send BD Initiator state machine has caused an attention. Fatal
30 Send BD Completion The Send BD Completion state machine has caused an
attention.
Fatal
29 Send BD Ring Selector The Send BD Ring Selector state machine has caused an
attention.
Fatal
28 Send Data Initiator The Send Data Initiator state machine has caused an
attention.
Fatal
27 Send Data Completion The Send Data Completion state machine has caused an
attention.
Fatal
26:24 Reserved – 0 Fatal
23 Recv BD Initiator The Recv BD Initiator state machine has caused an attention. Fatal
22 Recv BD Completion The Recv BD Completion state machine has caused an
attention.
Fatal
21 Recv List Placement The Recv List Placement state machine has caused an
attention.
Fatal