Broadcom BCM5722 - Table 253: Send BD Completion Control Registers; Table 254: Send BD Completion Mode Register (Offset 0 X1 C00)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Send BD Completion Control Registers Page 280
SEND BD COMPLETION CONTROL REGISTERS
SEND BD COMPLETION MODE REGISTER (OFFSET 0X1C00)
Table 253: Send BD Completion Control Registers
Offset Registers
0x1c00–0x1c03 Send BD Completion Mode.
0x1c04–0x1fff Reserved.
Table 254: Send BD Completion Mode Register (Offset 0x1C00)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Attn_Enable When this bit is set to 1, an internal attention is generated
when an error occurs.
0R/W
Reserved (BCM5906
only)
–0RO
1 Enable This bit controls whether the Send BD Completion state
machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely
halted, it remains one when read.
1R/W
0 Reset When this bit is set to 1, the Send BD Completion state
machine is reset. This is a self-clearing bit.
0R/W