Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Receive Data and Receive BD Initiator Control Registers Page 286
RECEIVE DATA AND RECEIVE BD INITIATOR CONTROL REGISTERS
RECEIVE DATA AND RECEIVE BD INITIATOR MODE REGISTER (OFFSET 0X2400)
Table 264: Receive Data and Receive BD Initiator Control Registers
Offset Registers
0x2400–0x2403 Receive Data and Receive BD Ring Initiator Mode
0x2404–0x2407 Receive Data and Receive BD Ring Initiator Status
0x2408–0x244f Reserved
0x2450–0x245f Standard Receive BD ring RCB
0x2460–0x2473 Reserved
0x2474–0x2477 Receive Diagnostic Data and Receive BD Ring Initiator Local NIC Standard Receive BD Consumer
Index
0x2478–0x247f Reserved
0x2480–0x2483 Receive Diagnostic Data and Receive BD Initiator Local Receive Return 1 Producer Index
0x2484–0x2487 Receive Diagnostic Data and Receive BD Initiator Local Receive Return 2 Producer Index
Reserved (BCM5906 only)
0x2488–0x248b Receive Diagnostic Data and Receive BD Initiator Local Receive Return 3 Producer Index
Reserved (BCM5906 only)
0x248c–0x248f Receive Diagnostic Data and Receive BD Initiator Local Receive Return 4 Producer Index
Reserved (BCM5906 only)
0x2490–0x27ff Reserved
Table 265: Receive Data and Receive BD Initiator Mode Register (Offset 0x2400)
Bit Field Description Init Access
31:5 Reserved – 0 RO
4 Illegal return ring size Enables illegal return ring size attention. R/W
3 Frame size is too large to fit
into one Receive BD
Enables frame size is too large to fit into one Receive BD attention. R/W
2 Reserved – 0 RO
1 Enable This bit controls whether the Receive Data and Receive BD Initiator
state machine is active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is completely halted, it
remains one when read.
R/W
0 Reset When this bit is set to 1, the Receive Data and Receive BD Initiator
state machine is reset. This is a self-clearing bit.
R/W
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