Broadcom BCM5722 - Table 116: VPD Capability ID Register (Offset 0 X50); Table 117: VPD Next Capabilities Pointer Register (Offset 0 X51); Table 118: VPD Flag and Address Register (Offset 0 X52)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Vital Product Data Capabilities Page 200
VITAL PRODUCT DATA CAPABILITIES
Devices that support Vital Product Data (VPD) Management must support a block of registers that is part of the Capabilities
List in PCI Configuration Space. The VPD Register Block is located at offset 0x50. The device supports the VPD registers
described in the following section.
VPD CAPABILITY ID REGISTER (OFFSET 0X50)
This 8-bit register identifies this item in the Capabilities List as a Vital Product Data (VPD) register set.
VPD NEXT CAPABILITIES POINTER REGISTER (OFFSET 0X51)
This register points to the next item in the Capabilities List.
VPD FLAG AND ADDRESS REGISTER (OFFSET 0X52)
The upper most bit (bit 15) of this register is a flag that indicates when the transfer between the VPD Data Register and the
storage component is completed. The lower 15 bits (14–0) of the register contain the byte address of the VPD to be
accessed.
Table 116: VPD Capability ID Register (Offset 0x50)
Bit Field Description Init Access
7:0 VPD Capability ID Identifies this item as Vital Product Data capabilities. 03h RO
Table 117: VPD Next Capabilities Pointer Register (Offset 0x51)
Bit Field Description Init Access
7:0 VPD Next Capabilities Points to the next capabilities block which is for Broadcom
Vendor-Specific Capability Item.
58h RO
Table 118: VPD Flag and Address Register (Offset 0x52)
Bit Field Description Init Access
15 Flag Indicates when the transfer between the VPD Data
Register and the storage component is completed. To read
VPD information, a 0 is written to the flag bit when the
address is written to the VPD Address Register. The
device will then set the flag bit to 1, once the four bytes of
data from the storage component have been transferred to
the VPD Data register.
To write VPD information, a 1 is written to the Flag bit. The
device will clear this bit when the data is written.
XR/W
14:0 VPD Address Contains the byte address of the VPD to be accessed.
Since the data register is four bytes in size, the address
must be aligned on a 32-bit boundary.
XR/W