Broadcom BCM5722 - Table 242: Send Data Completion Control Registers; Table 243: Send Data Completion Mode Register (Offset 0 X1000); Table 244: Post-DMA Command Exchange Register for TCP Segmentation (Offset 0 X1008)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Send Data Completion Control Registers Page 276
SEND DATA COMPLETION CONTROL REGISTERS
SEND DATA COMPLETION MODE REGISTER (OFFSET 0X1000)
POST-DMA COMMAND EXCHANGE REGISTER FOR TCP SEGMENTATION (OFFSET 0X1008)
Table 242: Send Data Completion Control Registers
Offset Registers
0x1000–0x1003 Send Data Completion Mode.
0x1004–0x1007 Reserved.
0x1008–0x100B Post-DMA Command Exchange for TCP Segmentation
0x100C–0x13FF Reserved.
Table 243: Send Data Completion Mode Register (Offset 0x1000)
Bit Field Description Init Access
31:2 Reserved – 0 RO
1 Enable This bit controls whether the Send Data Completion state machine
is active or not. When set to 0, it completes the current operation
and cleanly halts. Until it is completely halted, it remains one when
read.
1R/W
0 Reset When this bit is set to 1, the Send Data Completion state machine
is reset. This is a self-clearing bit.
0R/W
Table 244: Post-DMA Command Exchange Register for TCP Segmentation (Offset 0x1008)
Bit Field Description Init Access
31 PASS If this bit is set to 0, the CPU will be invoked to process the TXMBUF
data. It is the same as SDCQ bit 13.
1R/W
30 SKIP The CPU sets this bit to 1 to inform the SDC that the post-processing
is completed and the hardware can resume operation.
0R/W
29 End of
Fragmentation
End of Fragmentation. If this bit is set to 1, the SDC will requests the
HC to increment the Send Ring Consumer Index when the CPU sets
the SKIP bit. It is the same as SDCQ bit 12.
1R/W
28:12 Reserved – 0 RO
11:6 Head TXMBUF
Pointer
Head TXMBUF Pointer. They are the same as SDCQ bits 11:6. 0 R/W
5:0 Tail TXMBUF
Pointer
Tail TXMBUF Pointer. They are the same as SDCQ bits 5:0. 0 R/W