Broadcom BCM5722 - Flow Control Initialization Pseudocode; Integrated Macs; Table 90: Integrated MAC Flow Control Registers

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Flow Control Page 174
Integrated MACs
Table 90 lists the flow control registers in the BCM5722 Ethernet controllers.
FLOW CONTROL INITIALIZATION PSEUDOCODE
//Check the Link State
If (MII_Status_Reg.Link_Status == TRUE) Then
{
//Check PHY status register for full-duplex configuration
If (MII_Aux_Status_Reg.Auto_Neg_HCD ==
(1000_FULL_DUPLEX Or 100_FULL_DUPLEX Or 10_FULL_DUPLEX) ) Then
{
//Check if USER has forced either auto-negotiation or auto-advertise
If ( (Driver_Auto_Neg_Variable == ENABLED) And
(Driver_Auto_Advertise_Variable != FORCED_SPEED_DUPLEX )) Then
{
// Probe Phy control registers for advertised flow control info
// Expected abilities should match the configured abilities. Expected abilities
// are based on the IEEE 803.3ab flow control subsection.
If ( (Auto_Neg_Advertise_Reg.Asymetric_Pause != 802.3ab_Table_28B-3 ) And
(Auto_Neg_Advertise_Reg.Pause_Capable != 802.3ab_Table_28B-3 ) ) Then
{
//The current advertised state does not match 802.3 specifications
Driver_ Link__link_state = LINK_STATUS_DOWN
}
Else
{
If (Auto_Neg_Advertise_Reg.Pause_Capable == ENABLED)
{
If ( Auto_Neg_Advertise_Reg.Asymetric_Pause == ENABLED) ) Then
{
If (Auto_Neg_Link_Partner_Ability_Reg.Pause_Capable == ENABLED)
Then
{
Driver_Flow_Capability = FLOW_CONTROL_TRANSMIT_PAUSE \
| FLOW_CONTROL_RECEIVE_PAUSE
}
Else If (Auto_Neg_Link_Partner_Ability_Reg.Asymetric_Pause == \
ENABLED) Then
{
Table 90: Integrated MAC Flow Control Registers
Register Bit(s) Name Description Cross Reference
Receive MAC Mode Enable_Flow_Control Enable automatic processing of IEEE
802.3 flow control frames.
See “Receive MAC Mode
Register (Offset 0x468)” on
page 254.
Transmit MAC Mode Enable_Flow_Control Enable automatic processing of IEEE
802.3 flow control frames.
See “Transmit MAC Mode
Register (Offset 0x45C)” on
page 253.
MAC_RX_MBUF_
Low_Water_Mark
All 32 bits The number of internal buffers that must
be available before the RX engine can
accept a frame from the wire.
Threshold value for initiating flow control.
See “MAC RX MBUF Low
Watermark Register (Offset
0x4414)” on page 308.