Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R General Control Registers Page 336
MISCELLANEOUS LOCAL CONTROL REGISTER (OFFSET 0X6808)
The Miscellaneous Local Control register is used to control various functions within the device. All bits are set to zero (i.e.
disabled) during reset.
16:13 Bond ID ID(3:0) RO
12:8 Reserved – 00 RO
7:1 Timer Prescaler Local Core clock frequency in MHz, minus 1, which should
correspond to each advance of the timer. Reset to all 1.
Example: A 66-MHz local core clock uses 65 (0x41).
1111111 R/W
Reserved (BCM5906 only) – 0 RO
0 CORE Clock Blocks Reset
a
Write 1 to this bit resets the CORE_CLK blocks in the
device. This is a self-clearing bit.
0R/W
a. PCIe configuration cycles are non-posted transactions and require a completion to avoid a PCIe bus error. Drivers using
configuration cycles to do a GRC reset on PCIe devices need to give the device enough time to send out the configuration
write completion before the PCIe link goes down. The driver should slow the clock down by setting bits 20 (not 19) and 12 in
register 0x74 before issuing configuration cycles for a GRC reset (bit 0 of register 0x6804) or setting the PWRDOWN bit
(0x6804 bit 20). This is not required if PCIe reset is disabled during the GRC reset by setting the bit 29 of this register (0x6804)
to 1.
Table 344: Miscellaneous Local Control Register (Offset 0x6808)
Bit Field Description Init Access
31 Enable Wolink Up When set, the chip drives the PME when the link is up. 0 R/W
30 Enable Wolink Down When set, the chip drives the PME when the link is down. 0 R/W
29 Disable Traffic LED Fix
(CQ9609)
Set to 1 to disable Traffic LED Fix 0 R/W
28–27 Reserved – 0 RO
26 PME Assert (all other devices) When set, the PME Status bit in the PMSCR register (see
“PMCSR-BSE Register (Offset 0x4E)” on page 198) is forced
high. If PME Enable is also set, the PME
signal will activate. This
register bit is write-only and self-clearing after write.
0RO
25 Reserved – 0 RO
24 Auto SEEPROM Access If set, access to serial EEPROM goes through the serial
EEPROM address and data registers. Otherwise, serial
EEPROM control register should be used.
0R/W
23:17 Reserved – 0 RO
16:14 GPIO Pins [2:0] outputs Outputs which are defined by board level design. 0 R/W
13:11 GPIO Pins [2:0] output
enables
When asserted, the device drives miscellaneous pin outputs. 0 R/W
10:8 GPIO Pins [2:0] inputs Input from bidirectional miscellaneous pin. 0 RO
7 Global Interrupt Enable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
When this bit is set, the interrupt to the CPU is enabled. 0 R/W
Reserved (other devices) – 0 RO
6 Reserved – 0 RO
Table 343: Miscellaneous Configuration Register (Offset 0x6804) (Cont.)
Bit Field Description Init Access
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