Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R BCM5722 Ethernet Controller Register Definitions Page 186
Section 12: BCM5722 Ethernet Controller
Register Definitions
PCI CONFIGURATION REGISTERS
The following describes the registers required for configuration by the PCI, PCI-X, and PCIe specifications. Access to these
registers can be obtained through either the PCI Configuration address space, or through the shared-memory region of the
BCM5722 Ethernet controller. Some registers must be defined as read-only in the PCI Configuration address space, but are
allowed to be read/write when accessed by other means. A more detailed description of each register can be obtained from
both the PCI, PCI-X, and PCIe specifications. All reserved fields in the Configuration region return a 0 value on a read
operation. A write operation has no effect.
Note: Unless specified otherwise, all registers and bit fields in this section are applicable to all the BCM5722
Ethernet controllers covered in this document.
Table 92: PCI Configuration Register Summary
Offset Register
0x00–0x01 Vendor ID
0x02–0x03 Device ID
0x04–0x05 Command
0x06–0x07 Status
0x08 Revision ID
0x09–0x0B Class Code
0x0C Cache Line Size
0x0D Latency Timer
0x0E Header Type
0x0F BIST
0x10–0x13 Base Address register 1 (lower 32-bit)
0x14–0x17 Base Address register 2 (upper 32-bit)
0x18–0x28 Base Address registers 3–6
0x28–0x2B Reserved
0x2C–0x2D Subsystem Vendor ID
0x2E–0x2F Subsystem ID
0x30–0x33 Expansion ROM Base Address
0x34 Capabilities Pointer
0x35–0x3B Reserved
0x3C Interrupt Line
0x3D Interrupt Pin
0x3E MIN_GNT
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