BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 187 PCI Configuration Registers Document 5722-PG101-R
0x3F MAX_LAT
0x40–0x47 Reserved
0x48 Power Management Capability ID
0x49 Next Capability Pointer (VPD)
0x4A–0x4B Power Management Capabilities
0x4C–0x4D Power Management Control/Status
0x4E Reserved
0x4F Power Management Data
0x50 Vital Product Data Capability ID
0x51 Next Capability Pointer (MSI)
0x52–0x53 VPD Address/Flag
0x54–0x57 VPD Data
0x58–0x5B Broadcom Vendor-Specific Capability Header
0x5C–05F Reset Counters
0x60–0x67 Reserved
0x68–0x6B Miscellaneous Host Control
0x6C–0x6F DMA Read/Write Control
0x70–0x73 PCI State
0x74–0x77 PCI Clock Control
0x78–0x7B Register Base Address
0x7C–0x7F Memory Window Base Address
0x80–0x83 Register Data
a
0x84–0x87 Memory Window Data
0x88–0x8B Expansion ROM BAR Size
0x8C–0x8F Expansion ROM Address
0x90–0x93 Expansion ROM Data
0x94–0x97 VPD Interface
0x98–0x9F UNDI Receive BD Standard Ring Producer Index Mailbox
0xA0–0xA7 UNDI Receive Return Ring Consumer Index Mailbox
0xA8–0xAF UNDI Send BD Producer Index Mailbox
0xB0–0xB7 Interrupt Mailbox 0 (shadow, see “Interrupt Mailbox 0 Register (Offset 0x200–0x207)” on
page 238 for host standard and flat modes and “Interrupt Mailbox 0 Register (Offset
0x5800–0x5807)” on page 325 for indirect mode)
0xB8–0xCF Reserved
0xD0 PCIe Capability ID
0xD1 Next Capability Pointer
0xD2–0xD3 PCIe Capabilities
0xD4–0xD7 Device Capabilities
0xD8–0xD9 Device Control
Table 92: PCI Configuration Register Summary (Cont.)
Offset Register
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