Broadcom BCM5722 - Memory Arbiter Mode Register (Offset 0 X4000); Memory Arbiter Registers; Table 291: Memory Arbiter Registers; Table 292: Memory Arbiter Mode Register (Offset 0 X4000)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 301 Memory Arbiter Registers Document 5722-PG101-R
MEMORY ARBITER REGISTERS
MEMORY ARBITER MODE REGISTER (OFFSET 0X4000)
Table 291: Memory Arbiter Registers
Offset Registers
0x4000–0x4003 Memory Arbiter Mode
0x4004–0x4007 Memory Arbiter Status.
Reserved in BCM5906
0x4008–0x400b Memory Arbiter Trap Address Low
Reserved in BCM5906
0x400c–0x400f Memory Arbiter Trap Address High
Reserved in BCM5906
0x4010–0x43ff Reserved
Table 292: Memory Arbiter Mode Register (Offset 0x4000)
Bit Field Description Init Access
31:30 Reserved – 0 R/W
29 CPU pipeline request
disable
CPU pipeline request disable. When set to 1, the write/read
requests from the internal CPU will be processed sequentially
(i.e., no back to back data valid).
R/W
Reserved (BCM5906 only) –
28 Low Latency Enable Low Latency Enable.
• When set to 1, the read from the CPU to the RXMBUF will take
the original MA protocol, where data_rd_valid always goes after
cmd_ack.
• If set to 0, the data_rd_valid overlaps at the same clock cycle
as the cmd_ack.
0R/W
Reserved (BCM5906 only) –
27 Fast Path Read Disable Fast Path Read Disable. When set to 1, the read from the CPU to
the RXMBUF will take the slow path that goes through the original
memory arbitration logic.
R/W
Reserved (BCM5906 only) –
26:21 Reserved – 0 RO
20 DMAW2 Addr Trap Enable DMA Write 2 Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
17 Reserved – 0 RO
16 SDI Addr Trap Enable Send Data Initiator Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
15:13 Reserved – 0 R/W
12 RDI2 Addr Trap Enable Receive Data Initiator 2 Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
11 RDI1 Addr Trap Enable Receive Data Initiator 1 Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –