Broadcom BCM5722 - Page 361

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Memory Arbiter Registers Page 302
10 RQ Addr Trap Enable Receive List Placement Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
9 Reserved – 0 RO
8 PCI Addr Trap Enable PCI Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
7 Reserved – 0 RO
6 RX RISC Addr Trap Enable RX RISC Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
5 DMAR1 Addr Trap Enable DMA Read 1 Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
4 DMAW1 Addr Trap Enable DMA Write 1 Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
3 RX-MAC Addr Trap Enable Receive MAC Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
2 TX-MAC Addr Trap Enable Transmit MAC Memory Arbiter request trap enable. R/W
Reserved (BCM5906 only) –
1 Enable This bit controls whether the Memory Arbiter is active or not. When
set to 0, it completes the current operation and cleanly halts. Until
it is completely halted, it remains 1 when read.
R/W
0 Reset When this bit is set to 1, the Memory Arbiter state machine is
reset. This is a self-clearing bit.
R/W
Table 292: Memory Arbiter Mode Register (Offset 0x4000) (Cont.)
Bit Field Description Init Access