Broadcom BCM5722 - Table 150: MSI Capability ID Register (Offset 0 Xe8); Table 151: MSI Next Capabilities Pointer Register (Offset 0 Xe9)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 221 Message Signaled Interrupts Capabilities Document 5722-PG101-R
MESSAGE SIGNALED INTERRUPTS CAPABILITIES
Devices that support Message Signaled Interrupts (MSI) must support a block of registers that is part of the Capabilities List
in PCI Configuration Space. The MSI Register Block is located at offset 0xE8.
Typical use of MSI and, in particular, multiple MSIs is to allow multiple processors to receive interrupt information
independently of the others. The actual use of these in conjunction with the various send and receive queues and status
information is application dependent. The device supports the following MSI registers:
MSI CAPABILITY ID REGISTER (OFFSET 0XE8)
This 8-bit register identifies this item in the Capabilities List as a Message Signaled Interrupt (MSI) register set.
MSI NEXT CAPABILITIES POINTER REGISTER (OFFSET 0XE9)
This register points to the next item in the Capabilities List.
Table 150: MSI Capability ID Register (Offset 0xE8)
Bit Field Description Init Access
7:0 MSI Capability ID Identifies this item as Message Signaled Interrupt
capabilities.
05h RO
Table 151: MSI Next Capabilities Pointer Register (Offset 0xE9)
Bit Field Description Init Access
7:0 MSI Next Capabilities Points to the next capabilities block that is PCIe. 0xD0 RO