Broadcom BCM5722 - BCM5756 M, BCM5757, BCM5754, BCM5787 Only; BCM5757, BCM5754, BCM5787 Only; Table 293: Memory Arbiter Status Register (Offset 0 X4004)-BCM5722, BCM5755, BCM5755 M, BCM5756 M; Table 294: Memory Arbiter Trap Address Low Register (Offset 0 X4008)-BCM5722, BCM5755, BCM5755 M, BCM5756 M, BCM5757, BCM5754, BCM5787 Only

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 303 Memory Arbiter Registers Document 5722-PG101-R
MEMORY ARBITER STATUS REGISTER (OFFSET 0X4004)—BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 ONLY
MEMORY ARBITER TRAP ADDRESS LOW REGISTER (OFFSET 0X4008)—BCM5722,
BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 O
NLY
Table 293: Memory Arbiter Status Register (Offset 0x4004)—BCM5722, BCM5755, BCM5755M, BCM5756M,
BCM5757, BCM5754, BCM5787 Only
Bit Field Description Init Access
31:21 Reserved – 0 RO
20 DMAW 2 Addr Trap DMA Write 2 Memory Arbiter request trap. W2C
19:17 Reserved – 0 RO
16 SDI Addr Trap Send Data Initiator Memory Arbiter request trap. W2C
15:13 Reserved – 0 R/W
12 RDI2 Addr Trap Receive Data Initiator 2 Memory Arbiter request
trap.
W2C
11 RDI1 Addr Trap Receive Data Initiator 1 Memory Arbiter request
trap.
W2C
10 RQ Addr Trap Receive List Placement Memory Arbiter request
trap.
W2C
9 Reserved – 0 R/W
8 PCI Addr Trap PCI Memory Arbiter request trap. W2C
7 Reserved – 0 R/W
6 RX RISC Addr Trap RX RISC Memory Arbiter request trap. W2C
5 DMAR1 Addr Trap DMA Read 1 Memory Arbiter request trap. W2C
4 DMAW 1 Addr Trap DMA Write 1 Memory Arbiter request trap. W2C
3 RX-MAC Addr Trap Receive MAC Memory Arbiter request trap. W2C
2 TX-MAC Addr Trap Transmit MAC Memory Arbiter request trap. W2C
1:0 Reserved – RO
Table 294: Memory Arbiter Trap Address Low Register (Offset 0x4008)—BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757, BCM5754, BCM5787 Only
Bit Field Description Init Access
31:21 Reserved – 0 RO
20:0 MA Trap Addr Low Memory Arbiter Trap Address Low. R/W