Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 458
SPARE CONTROL 3 (PHY_ADDR = 0X1, REG_ADDR = 1CH, SHADOW 00101B)
Write Enable
During a write to this register, setting Spare Control 3 register bit 15 allows writing to bits [9:0] of this register. For reading
the values of bits [9:0], perform an MDIO write with bit 15 cleared and preferred Shadow register values in bits [14:10]. The
next MDIO read of register address 1Ch contains the preferred Shadow register values in bits [9:0].
Shadow Register Selector
Register bits [14:10] must be set to 00101 to enable read/write to the Spare Control 3 register.
CLK125 Auto Power Down
Clearing this bit enables the auto power down of the CLK125 output. This feature enables additional power savings. This
feature should only be used during auto power-down mode.
CLK125 Output
Setting this bit enables the CLK125 output; clearing this bit disables the CLK125 output.
Table 519: Spare Control 3 Register (Address 1Ch, Shadow Value 00101)
Bit Field Description Init Access
15 Write Enable • 1 = Write bits [9:0].
• 0 = Read bits [9:0].
0R/W
14:10 Shadow Register
Selector
00101 = Spare Control 3 Register. 00101 R/W
9:2 Reserved Write as 03h, ignore when read. 03h R/W
1 CLK125 Auto Power-
Down
• 1 = Auto power-down of CLK125 is disabled.
• 0 = Auto power-down of CLK125 is enabled.
1R/W
0 CLK125 Output
• 1 = Enable CLK125 output.
• 0 = Disable CLK125 output.
1R/W
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