Broadcom BCM5722 - Table 35: Recommended BCM5722 Ethernet Controller Memory Pool Watermark Settings; Table 36: Recommended BCM5722 Ethernet Controller Low Watermark Maximum Receive Frames Settings

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 85 Initialization Document 5722-PG101-R
28. Configure MAC memory pool watermarks. Broadcom has run hardware simulations on the Mbuf usage and strongly
recommends the settings shown in Table 35. These settings/values will establish proper operation for 10/100/1000
speeds. Host software must configure the MAC RX Mbuf Low Watermark and Mbuf High Watermark registers (“MAC RX
MBUF Low Watermark Register (Offset 0x4414)” on page 308, and “MBUF High Watermark Register (Offset 0x4418)”
on page 308) during initialization.
29. Configure flow control behavior when the Rx Mbuf low watermark level has been reached (see Table 36 and “Low
Watermark Maximum Receive Frames Register (Offset 0x504)” on page 258). See the note above in Step-28.
30. Enable the buffer manager. The buffer manager handles the internal allocation of memory resources for send and
receive traffic. The Enable and Attn_Enable bits should be set in the Buffer Manager Mode register (see “Buffer Manager
Mode Register (Offset 0x4400)” on page 306).
31. Poll for successful start of buffer manager. Poll the Enable bit in the Buffer Manager Mode register (see “Buffer Manager
Mode Register (Offset 0x4400)” on page 306) for 10 ms. This test ensures the buffer manager successfully starts from
the previous step. The Enable bit will remain de-asserted until the buffer manager starts, at which point it will reflect an
asserted state.
32. Enable internal hardware queues. The MAC architecture uses internal queues to pass messages between functional
blocks. These messages coordinate RX/TX traffic flows. Device drivers need to enable these queues so the hardware
blocks can pass messages. Host software must set and then reset the bits in the FTQ Reset register (see “FTQ Reset
Register (Offset 0x5C00)” on page 326) to start internal queues:
a. First, host software should write 0xFFFFFFFF to the FTQ Reset register.
b. Second, host software should clear the FTQ Reset register by writing 0x00000000.
33. Initialize the Standard Receive Buffer Ring. Host software should write the Ring Control Block structure (see “Ring
Control Blocks” on page 44) to the Standard Receive BD Ring RCB register (see “Standard Receive BD Ring RCB
Register (Offset 0x2450)” on page 287). Host software should be careful to initialize the host physical memory address
based on allocation routines specific to the OS/RTOS. Table 37 shows the recommended Standard Ring Initialization
settings.
Table 35: Recommended BCM5722 Ethernet controller Memory Pool Watermark Settings
Register Standard Ethernet Frames
MAC RX Mbuf Low Watermark 0x20
Mbuf High Watermark 0x60
Note: The Low WaterMark Max Receive Frames register (0x504) specifies the number of good frames to
receive after RxMbuf Low Watermark has been reached. The driver software should make sure that the MAC
RxMbuf Low WaterMark is greater than the number of Mbufs required for receiving the number of frames as
specified in 0x504. The first Mbuf in the Mbuf chain of a frame will have 80 bytes of packet data while each
of the subsequent Mbufs except the last Mbuf will have 120 bytes for packet data. The last Mbuf in the chain
will have the rest of the packet data which can be up to 120 bytes.
Table 36: Recommended BCM5722 Ethernet controller Low Watermark Maximum Receive Frames’
Settings
Register Bits Recommended Value
Low Water Mark Maximum Receive Frames All 2