Broadcom BCM5722 - Table 345: Timer Register (Offset 0 X680 C)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 337 General Control Registers Document 5722-PG101-R
TIMER REGISTER (OFFSET 0X680C)
The Timer register is a 32-bit free-running counter. In the BCM5906, this counter increments based on the 25-MHz clock.
For all others, this counter increments when the Prescale Counter hits the Timer Prescaler limit as specified by the
Miscellaneous Configuration register (see “Miscellaneous Configuration Register (Offset 0x6804)” on page 335). The CPU
uses this counter to keep track of relative time in microseconds. A write to the Timer register loads the counter value written.
5 Testclk_25_disable
(BCM5722, BCM5755,
BCM5755M, BCM5756M,
BCM5757 only)
25-MHz test clock disable 0 R/W
Reserved (other devices) – 0 RO
4 Gpio_uart_sel
(BCM5722, BCM5755,
BCM5755M, BCM5756M,
BCM5757 only)
GPIO[2:1] pins are shared with UART SDATA_O and SDATA_I
pins for the 100-pin FBGA package.
• 0 = Select UART for 11x11 FBGA package
• 1 = Select GPIO for 11x11 FBGA package
0R/W
Reserved (other devices) 0 RO
3 Interrupt on Attention If set, the host will be interrupted when any of the attention bits in
the CPU event register are asserted.
0R/W
2 Set Interrupt If Interrupt Mailbox 0 contains a nonzero value, setting this bit
does nothing. If Interrupt Mailbox 0 is zero, then setting this bit will
cause the internal unmasked interrupt state to be asserted. The
external interrupt state (INTA
pin) will also be asserted
immediately if interrupts are not masked by the Mask Interrupts
bit. If interrupts are masked, INTA
will be asserted once interrupts
are unmasked, so long as interrupts are not first cleared. This bit
is not operational in MSI mode.
0W/O
1 Clear Interrupt This bit provides the same functionality as the Clear Interrupt bit
in the Miscellaneous Host Control register. This bit is not
operational in MSI mode
0W/O
0 Interrupt State This bit reflects the state of the PCI INTA
pin. This bit is not
operational in MSI mode.
0RO
Table 345: Timer Register (Offset 0x680C)
Bit Field Description Init Access
31:0 Timer value 32-bit free-running counter. 0 R/W
Table 344: Miscellaneous Local Control Register (Offset 0x6808) (Cont.)
Bit Field Description Init Access