BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 37 PHY Control Document 5722-PG101-R
The specifics of MII may be located in section 22 of the IEEE 802.3 specification. RXD[3:0] are the receive data signals;
TXD[3:0] are the transmit data signals. MII operates at both 10-Mbps and 100-Mbps wire-speeds. (Gigabit Ethernet uses
the GMII standard.) When MAC and PHY are configured for 10 Mbps operation, the RX_CLK1 and MII_TXCLK clocks run
at 2.5 MHz. Both RX_CLK1 and MII_TXCLK are sourced by the PHY. 100-Mbps wire speed requires RX_CLK1 and
MII_TXCLK to provide a 25-MHz reference clock. Receive Data Valid (RX_DV) is asserted when valid frame data is
received; at any point during data reception, the PHY may assert Receive Error (RX_ER) to indicate a receive error. The
MAC will record this error in the statistics block. The MAC may discard a bad RX frame—exception being sniffer/
promiscuous modes (see Allow_Bad_Frames bit in MAC mode register). The Transmit Enable (TX_EN) signal is asserted
when the MAC presents the PHY with a valid frame for transmission. The MAC may assert TX_ER to indicate the remaining
portion of frame is bad. The PHY will insert Bad Code symbols into the remaining portion of the frame. A detected collision
in half-duplex mode may be such a scenario where TX_ER is asserted. The PHY will assert COL when a collision is detected.
The COL signal is routed to both the RX and TX MACs. The transmit MAC will back off transmission and the RX MAC will
throw away partial frames.
The 10 Mbps physical layer uses Differential Manchester encoding on the wire. Manchester encoding uses two encoding
levels: 0 and 1. 100 Mbps Ethernet requires MLT-3 waveshaping on the transmission media. MLT-3 uses three encoding
levels: -1, 0, and 1. Both physical signaling protocols are transparent to the MAC sublayer and are digitized by the PHY. The
PHY encodes/decodes analog waveforms at its lower edge while the PHY presents digital data at its upper edge (MII).
GMII BLOCK
The GMII is full-duplex (see Figure 19 on page 38); the send and receive data paths operate independently.
The transmit signals TXD[7:0] create a eight-bit wide data path. The TXD[7:0] signals are synchronized to the reference
clockTX_CLK0. The TX_CLK0 clock runs at 125 MHz and is sourced by the MAC sublayer. Transmit Error (TX_ER) is
asserted by the MAC sublayer. The PHY will transmit a bad code until TX_ER is de-asserted by the MAC. TX_ER is driven
synchronously with TX_CLK0. The Transmit Enable (TX_EN) indicates that valid data is presented on the TXD lines. The
TXD[7:0] data is framed on the rising edge of TX_EN.
The receive data path is also eight bits wide. RXD[7:0] are sourced by the PHY. When valid data is presented to the MAC
sublayer, the PHY will also assert Receive Data Valid (RX_DV). The rising edge of RX_DV indicates the beginning of a frame
sequence. The PHY drives the reference clock RX_CLK1, so the MAC sublayer can synchronize data sampling on RXD[7:0].
The PHY may assert RX_ER to indicate frame data is invalid; the MAC sublayer must consider frames in progress
incomplete.
When the MAC operates in half-duplex mode, a switch or node may transmit a jamming pattern. The PHY will drive the
Collision (COL) signal so the MAC may back off transmission and throw away partially received packet(s). The COL signal
will also cause the TX MAC to stop the transmission of a packet. The COL signal is not driven for full-duplex operation since
collisions are undefined. The PHY will drive Carrier Sense (CRS) as a response to traffic being sent/received. The MAC
sublayer can monitor traffic and subsequently drive traffic LEDs.
To Next Page
Loading...