BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 227 PCIe-Enhanced Capabilities Document 5722-PG101-R
CORRECTABLE ERROR STATUS REGISTER (OFFSET 0X110)
CORRECTABLE ERROR MASK REGISTER (OFFSET 0X114)
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER (OFFSET 0X118)
Table 159: Correctable Error Status Register (Offset 0x110)
Bit Field Description Init Access
31:13 Reserved – 0 RO
12 Replay Timer Timeout
Status
This bit is set when a Replay Timer Timeout error occurs. 0 W2C
11:9 Reserved – 0 RO
8 REPLAY_NUM
Rollover Status
This bit is set when a REPLAY_NUM Rollover error
occurs.
0W2C
7 Bad DLLP Status This bit is set when a Bad DLLP error occurs. 0 W2C
6 Bad TLP Status This bit is set when a Bad TLP error occurs. 0 W2C
5:1 Reserved – 0 RO
0 Receiver Error Status This bit is set when a Receiver error occurs. 0 W2C
Table 160: Correctable Error Mask Register (Offset 0x114)
Bit Field Description Init Access
31:14 Reserved – 0 RO
13 Advisory Non-Fatal
Error Mask
This bit is set by default to enable compatibility with
software that does not comprehend Role-Based Error
Reporting.
1R/W
12 Replay Timer Timeout
Mask
Setting this bit will mask Replay Timer Timeout errors. 0 R/W
11:9 Reserved – 0 RO
8 REPLAY_NUM
Rollover Mask
Setting this bit will mask REPLAY_NUM Rollover errors. 0 R/W
7 Bad DLLP Mask Setting this bit will mask Bad DLLP errors. 0 R/W
6 Bad TLP Mask Setting this bit will mask Bad TLP errors. 0 R/W
5:1 Reserved – 0 RO
0 Receiver Error Mask Setting this bit will mask Receiver errors. 0 R/W
Table 161: Advanced Error Capabilities and Control Register (Offset 0x118)
Bit Field Description Init Access
31:9 Reserved – 0 RO
8 ECRC Check Enable Setting this bit will enable ECRC checking. 0 R/W
7 ECRC Check Capable When this bit is set, it indicates that this device supports
ECRC Checking.
1RO
6 ECRC Generation
Enable
Setting this bit will enable ECRC generation. 0 R/W
5 ECRC Generation
Capable
When this bit is set, it indicates that this device supports
ECRC generation.
1RO
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