Broadcom BCM5722 - Power Control)

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BCM5722 Programmer’s Guide

10/15/07

Broadcom Corporation

Page 447 Transceiver Registers Document 5722-PG101-R

AUXILIARY CONTROL REGISTER (PHY_ADDR = 0X1, REG_ADDR = 18H, SHADOW = 010,

OWER CONTROL)

5 SQE Enable Mode Writing a 1 to this bit enables SQE mode. Writing a 0 disables

it.This bit is valid only during 10BASE-T operation.

• 1 = Enable SQE.

• 0 = Disable SQE.

0R/W

4 10BASE-T No Dribble When enabled, the PHY rounds down to the nearest nibble

when dribble bits are present on the 10BASE-T input stream.

• 1 = Correct 10BASE-T dribble nibble.

• 0 = Normal operation.

0R/W

3 Reserved 0RO

2:0 Shadow Register

Select

The Auxiliary Control Register provides access to eight

registers using a shadow technique. These three bits written

define which set of 13 upper bits is used. No setup is

required. Register reads are determined by the previous

write operation.

• 000 = Normal Operation

• 001 = 10 BASE-T Register.

• 010 = Power Control Register

• 011 = Reserved.

• 100 = Misc Test Register 1

• 101 = Misc Test Register 2

• 110 = Reserved.

• 111 = Misc Control Register

000 R/W

Table 510: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 010,

Power Control)

Bit Field Description Init Access

15:6 Reserved – 00Eh R/W

5 Super Isolate N/A 0 R/W

4:3 Reserved Write as 1, ignore on read. 10 R/W

2:0 Shadow Register

Select

The Auxiliary Control Register provides access to eight

registers using a shadow technique. These three bits

written define which set of 13 upper bits is used. No setup

is required. Register reads are determined by the

previous write operation.